Modular Register Mapping Firmware Versions
| ID | Date | Changes |
|---|---|---|
| 0x1H000000 | EVR: First prototype release | |
| 0x1H000001 | 13.11.2007 | EVR: First production release |
| 0x1H000002 | 04.03.2008 | EVR: Added filter that allows forwarding received events on the TX port Added stop logic to FIFO |
| 0x1H000003 | 03.10.2008 | EVR: New Event Log that stores up to 512 events in a ring buffer. The stop logic has been moved from the Event FIFO to the log. So the FIFO remains as it was before the stop logic change. The external inputs now have configurable edge and level sensitivity |
| 0x20000001 | 13.07.2007 | EVG: First production version |
H) denotes form factor: 0 – CompactPCI 3U, 1 – PMC, 2 – VME, 3 – CompactRIO, 4 – CompactPCI 6U
VME-EVR-200 and VME-EVR-RF-200
| ID | Date | Changes |
|---|---|---|
| 0xD309 | 05.06.2006 | Disable front panel outputs by default |
| 0xD30A | 03.12.2007 | Fixed issue with the timestamp being latched incorrectly occasionally when the timestamp was latched and incremented simultaneously. Added read-only rx_link_ok signal to bit 3 of the control/status register to show link status. |
VME-EVG-230
| ID | Date | Changes |
|---|---|---|
| 0xE402 | 10.03.2009 | Added support for programmable front panel inputs and Universal I/O inputs |
| 0xE403 | 28.07.2009 | Fixed MXC synchronization bug that occasionally misaligned the counters by one cycle |
VME-EVR-230
| ID | Date | Changes |
|---|---|---|
| 0xD502 | 13.04.2007 | Initial release Added interlock input to front panel UNIV0. |
| 0xD504 | 03.01.2008 | Fixed issue with the timestamp being latched incorrectly occasionally when the timestamp was latched and incremented simultaneously. Added read-only rx_link_ok signal to bit 3 of the control/status register to show link status. |
| 0xD505 | 18.05.2009 | Added interlock latching support. |
| 0xD506 | 11.08.2009 | Fixed writing of polarity bit of transition board output OTP13. |
VME-EVR-230RF
| ID | Date | Changes |
|---|---|---|
| 0xD501 | 07.11.2006 | Initial release |
| 0xD502 | 07.06.2007 | Added interlock input to front panel UNIV0. Added front panel Universal I/O GPIO pins to allow setting delay on UNIV-LVPECL-DLY modules. |
| 0xD503 | 10.08.2007 | Added configuration of CDR to disable harmonic detector. The harmonic detector causes the CDR to trigger a new frequency acquisition when the bi rate is less than 2.5 Gbit/s and full 2k buffers are transmitted causing a los of link. |
| 0xD504 | 03.12.2007 | Fixed issue with the timestamp being latched incorrectly occasionally when the timestamp was latched and incremented simultaneously. Added read-only rx_link_ok signal to bit 3 of the control/status register to show link status. |
| 0xD505 | 11.05.2009 | Added interlock latching support. |
| 0xD506 | 11.08.2009 | Fixed writing of polarity bit of transition board output OTP13. |
| 0xD507 | 19.02.2010 | Added frequency output mode to CML outputs |